1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Related Art
Conventionally, there has been known a configuration in which a cap layer having a function as a copper diffusion barrier is formed on copper interconnect lines in a semiconductor device including the copper interconnect lines. There is disclosed a semiconductor device with a configuration in a Japanese Laid-open patent publication No. 2003-243392, wherein a cap layer is formed on metal interconnects including copper, and the cap layer has a silicide surface according to the configuration. According to the Japanese Laid-open patent publication No. 2003-243392, it is possible to effectively prevent oxidation and erosion by hydrofluoric acid by the configuration in which the cap layer has the silicide surface.
According to Japanese Laid-open patent publication No. 2003-100746, there is disclosed processing in which there are included a step of forming a conductive film on a whole surface of a semiconductor substrate, wherein the film is embedded in a concave pattern; a step of removing the conductive film in regions other than those of the concave pattern; a step of forming a conductive cap layer on the conductive film by selective growth or preference growth; and a step of removing extraneous matters on the surface of an insulating film by Chemical Mechanical Polishing (CMP) thereafter. According to Japanese Laid-open patent publication No. H9-064034, steps according to which an interconnect material layer is anisotropically deposited, a surface protection layer is formed on the whole surface, and, thereafter, a diffusion barrier, an interconnect layer, and the surface protection layer, other than those for an interconnect trench, are removed by the CMP method, an etching back method, and the like, are described.
FIG. 4 is a flow chart showing a manufacturing procedure for manufacturing a conventional semiconductor device with a cap layer. Moreover, FIGS. 5A to 5E are a cross-sectional view of the conventional semiconductor device at each step in the manufacturing procedure. Hereinafter, the manufacturing procedure of the conventional semiconductor device will be explained, referring to FIG. 4 and FIGS. 5A to 5E.
Firstly, an interconnect trench 13 is formed in an insulating interlayer 12 formed on a semiconductor substrate (not shown) (FIG. 5A corresponding to a step S10 shown in FIG. 4). Subsequently, a barrier metal layer 14 and a copper layer 16 are formed on a whole surface of the semiconductor substrate (FIG. 5B corresponding to step S12 and S14 shown in FIG. 4). The barrier metal layer 14 may include, for example, TaN, Ta, Ti, TiN, W, WN, and the like. The copper layer 16 may be formed as described hereafter. In the first place, a copper seed layer is formed by a Chemical Vapor Deposition (CVD) method or by a physical vapor deposition (PVD) method. Subsequently, the copper layer is formed by electroplating, and is embedded in the interconnect trench 13.
Then, the copper layer 16 and the barrier metal layer 14, which have been exposed in the outside of the interconnect trench 13, are removed by the CMP method (FIG. 5C corresponding to a step S16 shown in FIG. 4). Thereby, copper interconnect lines are formed. Thereafter, a cap metal layer 18 is selectively formed on the copper layer 16 by electroless plating (FIG. 5D corresponding to a step S18 shown in FIG. 4). Here, the cap metal layer 18 may include, for example, CoWP.
Subsequently, an insulating interlayer 20 is formed on a whole surface of the semiconductor substrate (FIG. 5E corresponding to a step S20 shown in FIG. 4).
FIG. 6 is a schematic cross-sectional view showing the configuration of a semiconductor device 10 which has been manufactured according to the above-described procedure. Here, the insulating interlayer 20, an insulating interlayer 26, and an insulating interlayer 34 are formed on the insulating interlayer 12. A via including a barrier metal layer 22 and a via layer 24 is formed in the insulating interlayer 20. An interconnect including a barrier metal layer 28 and a copper layer 30a, and an interconnect including the barrier metal layer 28 and a copper layer 30b are formed in the insulating interlayer 26. A cap metal layer 32a is formed on the copper layer 30a, and a cap metal layer 32b is formed on the copper layer 30b. 
As shown in FIG. 6, each grain has a different orientation, for example, (111), (200) or (110), in the copper layer 16. Therefore, the grains with different orientations from each other are exposed on the surface of the copper layer 16. When the orientation on the surface of the copper layer 16 is not uniform, there may occur a variation in the formation of the cap metal layer 18 formed thereon depending on a difference in the orientation to cause a difference in the layer thickness. In order to prevent copper diffusion in the copper layer 16, and deterioration in the reliability of Electro-Migration (EM), Stress Induced Void (SIV), and the like of the copper layer 16, it is required to securely cover the whole surface of the copper layer 16 with the cap metal layer 18. Accordingly, it is required to cover the copper layer with the cap metal layer 18 even in a region in which the cap metal layer 18 is hardly formed. That is, the layer thickness becomes thicker in a region in which the cap metal layer 18 is formed in an easier manner. When the layer thickness of the cap metal layer 18 becomes thicker, the resistance of a via formed on the layer 18 is increased.
FIG. 6 shows the cross section including the orientation (111) in the copper layer 30a, and the cross section including the orientation (200) in the copper layer 30b. In the above case, the layer thickness of the cap metal layer 32a and that of the cap metal layer 32b, wherein the cap metal layers are formed on the corresponding interconnect, depend on the orientation of the copper layer under the corresponding cap metal layer. When the layer thickness is not made uniform between the cap metal layer 32a and the cap metal layer 32b as described above, a variation in the via resistances is caused.
Moreover, when the insulating interlayer is deposited on the cap metal layer 18 under a state in which the surface of the cap metal layer 18 has irregularities, there is caused a problem that the flatness of the semiconductor device 10 is deteriorated.
There is caused a similar problem to that of the above case even in the semiconductor device disclosed in the Japanese Laid-open patent publication No. 2003-243392, because, when the surface of the cap metal layer has irregularities, the silicide surface of the semiconductor device is affected by the surface irregularity of the cap metal layer. In addition, when the cap metal layer is formed on the insulating interlayer, the reliability is deteriorated.
Moreover, a metal material of the cap metal layer 18 may adhere to the surface of the insulating interlayer 12 (black points in FIGS. 5D and 5E) in the steps for forming the cap metal layer 18. When the metal material adheres to the surface of the insulating interlayer 12, a short is caused between interconnects, or the reliability of Time Dependent Dielectric Breakdown (TDDB) and the like is deteriorated.
According to the processing described in the Japanese Laid-open patent publication No. 2003-100746, an extraneous matter on the surface of the insulating film is removed after the cap metal layer is formed. Therefore, the number of steps is increased. Moreover, it is difficult to completely remove the extraneous matter on the surface of the insulating film.